A integrated circuit (IC) process technology advances to higher densities, the feature size of a transistor is reduced enabling low-voltage high speed operation and high density layout. Another result of the reduced feature size is to also reduce the transistor's gate oxide voltage tolerance. Some conventional input/output (I/O) standards require an IC to interface with external voltages that are higher than the internal voltages used within the IC. Thus, it is necessary to interface low-voltage transistors to high voltage systems. This is an important challenge in input/output (I/)O design.
An exemplary conventional output buffer architecture with high voltage protection is shown in FIG. 1. In FIG. 1, an output stage 110 comprising a first transistor 111, a second transistor 112, a third transistor 113, and a fourth transistor 114 coupled in a cascode configuration is coupled with a level shifting circuit 120 and an output 140. Level shifting circuit 120 translates the internal CMOS voltage level to a voltage level which is conveyed to pullup bar output (PUB) 131 and pulldown output (PD) 134. Since the level shifting circuit 120 is operating under external voltage levels, high voltage protection is necessary for transistors inside this level shifting circuit 120 as well.
Transistors 111 and 114 are coupled with a pullup bar (PUB) output 131 and a pulldown (PD) output 134 respectively which convey signals from level shifting circuit 120. Transistors 112 and 113 are coupled with a pbias output 132 and an nbias output 133 respectively and provide protection from high voltage inputs and prevent the pullup bar (PUB) 131 and pulldown (PD) 134 signals from going above 2.5 volts (2.5V).
A conventional implementation of a cascode level-shifting circuit (e.g., level shifting circuit 120) is shown in FIG. 2. In FIG. 2, level shifting circuit 120 comprises transistors 210, 211, 212, and 213 coupled in a cascode configuration. Transistors 215, 216, 217, and 218 are also configured in a cascode configuration. Transistors 210 and 215 are coupled as a cross coupled latch and an external voltage (e.g., Vext 220) is coupled with the drain of transistor 210 and the drain of transistor 215. A pbias input (e.g., pbias 132 of FIG. 1) is coupled with the gate of transistor 211 and the gate of transistor 216. An nbias input (e.g., nbias signal 133 of FIG. 1) is coupled with the gate of transistor 212 and with the gate of transistor 217. An input voltage 230 is coupled with the gate of transistor 218 and with the input of inverter 240. The output of inverter 240 is coupled with the gate of transistor 213. The sources of transistors 213 and 218 are coupled with a ground.
To protect the internal circuitry of level shifting circuit 120, the voltage level of PUB 110 must meet certain conditions. One condition is that the voltage conveyed via PUB 131 must be greater than the sum of pbias 132 and the absolute value of Vtp where Vtp is the threshold value of a pmos transistor (e.g., transistor 211 of FIG. 2). A second condition is that pbias 132 must be greater than the difference between the external voltage (e.g., Vext 220) and the stress voltage (Vstress) of the transistors to avoid overstress. Equations of the above conditions are shown below:PUB>pbias+(Vtp)  (1)pbias>Vext−Vstress  (2)Combining the two above conditions yields a third equation shown below:PUB>Vext-Vstress+(Vtp)  (3).
Applying equation 3 to a 2.5V field effect transistor (FET) operating with a 3.3V supply voltage, the lowest output voltage level, also referred to as “voltage output low” (VOL) conveyed by PUB 131 is >3.3V−2.5V+0.6V. Thus the lowest output voltage level conveyed via PUB 131>1.4V. This voltage level is limited because pbias 132 and nbias 113 are maintained at a static voltage level of 0.8V. However, this voltage level is not low enough to fully turn on transistor 111 which is controlled by PUB 131. As a result, the pullup current output by output stage 110 via output 140 can be too low, thus restricting the speed of input/output (I/O) operations of the output buffer.